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CH7ġ1 Truth Table of D Latch The truth table for the D latch summarizes its operation. S R EN Q CH7ġ0 D Latch The D latch is an variation of the S-R latch but combines the S and R inputs into a single D input as shown: D Q Q D EN EN Q Q A simple rule for the D latch is: Q follows D when the Enable is active. Q R Solution Keep in mind that S and R are only active when EN is HIGH. S Q EN Example Show the Q output with relation to the input signals.
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The gated latch has an additional input, called enable (EN) that must be HIGH in order for the latch to respond to the S and R inputs. Q 1 R CH7Ī gated latch is a variation on the basic latch. Latch initially SET 1 Never apply an active set and reset at the same time (invalid). Latch initially RESET 1 Q 1 R 1 S 1 Q To RESET the latch a momentary LOW is applied to the R input while S is HIGH. To SET the latch (Q = 1), a momentary LOW signal is applied to the S input while the R remains HIGH. 1 S 1 Q Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (1). 1 CH7Ĩ S-R Latch (cont.) The active-LOW S-R latch is in a stable (latched) condition when both inputs are HIGH. Latch initially RESET 1 R S Q 1 Latch initially SET To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW. To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW. R S Q 1 Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0).
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R S Q Q Q Q R S NOR Active-HIGH Latch NAND Active-LOW Latch CH7ħ S-R Latch The active-HIGH S-R latch is in a stable (latched) condition when both inputs are LOW. It can be constructed from NOR gates or NAND gates. The S-R (Set-Reset) latch is the most basic type. CH7ĥ Introduction (cont.) Synchronous VS AsynchronousĪll state transitions are controlled by a common clock Changes in all variables occur concurrently State transitions occur independently of any clock Changes in all variables do not necessarily occur concurrently CH7Ħ Latches A latch is a temporary storage device that has two stable states (bistable). In fact we can classify into two main classes :- Output can depend on the past and present inputs/outputs. Serial In/Serial Out Shift Registers Serial In/Parallel Out Shift Registers Parallel In/Serial Out Shift Registers Parallel Out/Parallel Out Shift Registers Bidirectional Shift Registers Shift Register Counters Shift Register Applications Conclusions CH7Ĥ Introduction Well, what u learned before is just one class of digital circuits. Operating Characteristics and Application Asynchronous Counter Synchronous Counter Cascaded Counters Counter Decoding Counter Applications Conclusions CH7ģ Contents Basic Shift Register Functions 1 Sequential Circuits: Flip-Flops and Counter By Taweesak ReungpeerakulĬhapter 5 Sequential Circuits: Flip-Flops and Counter By Taweesak Reungpeerakul CH7Ģ Contents Introduction Latches Edge-Triggered Flip-Flops (ET-FFs)